Design of Reconfigurable and Scalable Optical Interconnection Networks for Balanced Parallel Computing Systems
Project Description
The dramatic scaling and improvements in complementary metal-oxide semiconductor (CMOS) technology, coupled with innovations in computer architecture, have created an information technology society and a national economy very much dependent on a steady exponential growth in computing power. Near-term projections call for high-performance computing (HPC) systems with computing power in the hundreds of Teraflops, and aggregate communication bandwidth around 40 Terabits per second (Tbps). For these systems to be scalable and reach the needed performance, the interconnection network connecting the processors, must itself be scalable in both size and bandwidth. The interconnection network must not only deliver communication bandwidth and cost that grow linearly with the increase in the number of processors, but must also maintain a low overall latency. However, as feature sizes decrease to the sub-micron regime, and clock rates increase to the multi-GHz range, electrical interconnects are predicted to reach their fundamental limits and become the ultimate bottleneck for performance due to skin effect, crosstalk, interference, dielectric imperfections, attenuation, clock skew, and high power requirements. The major bottleneck is the limited bandwidth at higher bit rates and longer communication distances. This limitation, if not dealt with, will create major bandwidth imbalances in future HPCs, and will significantly affect their performance and scalability. It is widely accepted that performance improvements for HPC systems will require the introduction of new interconnect technologies to be integrated with CMOS processor design into new balanced architectures. One of the technologies that has been recognized to have the potential to solve communication problems of HPC systems is optical interconnects. Optical interconnects could lead to wiring design simplification, reduction in power requirements, ample communication bandwidth, and lower communication latency.
This research explores the application of optical technology to the communication problems of future HPC systems. The goal is to develop flexible and dynamically reconfigurable optical interconnection architectures that will scale to a large number of processors while delivering scalable bandwidth, low communication latency, low power consumption, and low cost. Reconfigurability will be realized by monitoring communication traffic intensities, and dynamically re-allocating bandwidth to adapt to changes in traffic patterns. The proposed architectures will also provide dynamic power management in order to optimize power consumption and lower communication costs. The proposed approach is an organized effort combining architecture, technology, simulation and physical demonstration. To achieve our goal, we propose a methodology that will: (1) provide ample communication bandwidth by exploiting key properties of optical technology, namely wavelength division multiplexing (WDM), and spatial division multiplexing (SDM), combining them into a Multi-WDM (M-WDM) technique and its extension to a Parallel-Multiple WDM (PM-WDM) scheme, (2) rely on power-efficient optical components and switches, thereby reducing power dissipation, minimizing cost and speeding up communication, and (3) exploit dynamic bandwidth re-allocation and power management techniques to provide full reconfigurability and optimized performance. The proposed research consists of three inter-related tasks :
(1) Development and design of reconfigurable and scalable optical interconnection architectures for HPCs,
(2) Identification and characterization of possible optical components necessary for the implementation of the proposed architectures and their integration with current HPC systems,
(3) Development of analytic modeling and simulation tools for the precise physical modeling of the optical implementation techniques, as well as end-to-end system modeling of the proposed architectures.
Publications
A. K. Kodi and A. Louri, “Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems,” in IEEE Micro, vol. 28, no. 5, pp. 22-36, Sept.-Oct. 2008.
A. K. Kodi and A. Louri, “System simulation methodology of optical interconnects for high-performance computing systems,” in Journal of Optical Networking, vol. 6, no. 12, pp. 1282-1300, Dec. 2007.
A. Kodi and A. Louri, “Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems,” Supercomputing, 2007. SC ‘07. Proceedings of the 2007 ACM/IEEE Conference on, Reno, NV, 2007, pp. 1-12.
C. Kochar, A. Kodi and A. Louri, “Proposed Low-Power High-Speed Microring Resonator-Based Switching Technique for Dynamically Reconfigurable Optical Interconnects,” in IEEE Photonics Technology Letters, vol. 19, no. 17, pp. 1304-1306, Sept. 2007.
C. Kochar, A. Kodi and A. Louri, “Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators,” in Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), Stanford, CA, 2007, pp. 54-64.
C. Kochar, A. K. Kodi and A. Louri, “nD-RAPID: A multidimensional scalable fault-tolerant optoelectronic interconnection for high-performance computing systems,” in Journal of Optical Networking, Special Issue on Switching in Photonics, vol. 6, no. 5, pp. 465-481, May 2007.
A. K. Kodi and A. Louri, “Power-Aware Bandwidth-Resonatorsconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems,” in Proceedings of the 2007 IEEE International Parallel and Distributed Processing Symposium, Long Beach, CA, 2007, pp. 1-10.
A. K. Kodi and A. Louri, “RAPID for high-performance computing systems: architecture and performance evaluation,“in Applied Optics, Special Issue on Information Photonics, vol. 45, no. 25, pp. 6326-6334, Sept. 2006.
A. K. Kodi and A. Louri, “
A. K. Kodi and A. Louri, “Switchless Photonic Architecture for Parallel Computers,” in Proceedings of Frontiers in Optics 2005, Tucson, AZ, 2005, pp. 1-1.
A. K. Kodi and A. Louri, “Scalable optical interconnection network for parallel and distributed computing,” in Proceedings of the 2005 OSA Topical Meeting on Information Photonics (IP), Charlotte, NC, 2005, pp. 1-3.
A. K. Kodi and A. Louri, “Design of a high-speed optical interconnect for scalable shared-memory multiprocessors,” in IEEE Micro, vol. 25, no. 1, pp. 41-49, Jan.-Feb. 2005.
A. K. Kodi and A. Louri, “RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors,” in Journal of Lightwave Technology, vol. 22, no. 9, pp. 2101-2110, Sept. 2004.
A. K. Kodi and A. Louri, “Design of a high-speed optical interconnect for scalable shared memory multiprocessors,” in Proceedings of the 12th Annual IEEE Symposium on High Performance Interconnects, Stanford, CA, 2004, pp. 92-97.
A. K. Kodi and A. Louri, “A scalable architecture for distributed shared memory multiprocessors using optical interconnects,” in Proceedings of the 18th International Parallel and Distributed Processing Symposium, Santa Fe, NM, 2004, pp. 1-10.