Farhadur Reza research interest include high-performance many-core architecture, energy efficient networks- on-chip, resource management and optimization, and machine learning techniques.
Welcome to HPCAT
We rely on computing in the design of systems for energy, transportation, finance, education, health, defense, entertainment, and overall wellness. However, today's computing systems are facing major challenges both at the technology and application levels. At the technology level, traditional scaling of device sizes has slowed down and the reduction of cost per transistor is plateauing, making it increasingly difficult to extract more computer performance by employing more transistors on-chip. Power limits and reduced semiconductor reliability are making device scaling more difficult – if not impossible – to leverage for performance in the future and across all platforms, including mobile, embedded systems, laptops, servers, and datacenters. Simultaneously, at the application level, we are entering a new computing era that calls for a migration from an algorithm computing world to a learning-based, data-intensive computing paradigm in which human capabilities are scaled and magnified. To meet the ever-increasing computing needs and to overcome power density limitations, the computing industry has embraced parallelism (parallel computing) as the only method for improving computer performance. Today, computing systems are being designed with tens to hundreds of computing cores integrated into a single chip and hundreds to thousands of computing servers based on these chips are connected in datacenters and supercomputers. However, power consumption remains a significant design problem, and such highly parallel systems still face major challenges in terms of energy efficiency, performance, and reliability.
Professor Louri and his team investigate novel parallel computer architectures and technologies which deliver high reliability, high performance, and energy-efficient solutions to important application domains and societal needs. The research has far-reaching impacts on the computing industry and society at large. Current research topics include: (1) the use of machine learning techniques for designing energy-efficient, reliable multicore architectures, (2) scalable accelerator-rich reconfigurable heterogeneous architectures, (3) emerging interconnect technologies (photonic, wireless, RF, hybrid) for network-on-chips (NoCs) & embedded systems, (4) future parallel computing models and architectures including Convolutional Neural Networks (CNNs), Deep Neural Networks (DNNs), near data computing, approximate computing, and (5) cloud and edge computing.
Machine Learning for High Performance Reliable NoCs
With continued aggressive technology scaling, Network-on-Chips (NoCs) architectures are facing three major challenges including minimizing power consumption, scaling performance, providing a reliable and robust communication. (more…)
Energy-Efficient Scalable Multicore Architectures
Over the last decade, Moore’s Law has slowed, while Dennard Scaling has ended. The end of voltage scaling has made power dissipation the fundamental barrier to scaling computing performance across all platforms. (more…)
Neural Networks Accelerator and Applications
Neural networks (NNs) have been successfully implemented in modern artificial intelligence (AI) applications ranging from image processing to speech recognition to natural language processing. (more…)
Approximate Communications
Recent research has shown that on-chip data movement consumes much more power than computation and this trend will continue in the future. Additionally, some algorithms and applications, such as machine learning… (more…)
Accelerator-Rich Heterogeneous Architectures
In the dark silicon era, only a fraction of transistors on a chip can be switched simultaneously due to constrained power budget. To improve energy-efficiency, general-purpose cores are augmented with specialized hardware or accelerators. (more…)
Emerging Interconnect Technologies for NOCS
There is a shift from multi-core to many-core architectures containing hundreds to a thousand cores on a single chip. However, traditional on-chip metallic interconnects require excessive power as technology keeps scaling. (more…)
- Optical Multi-Mesh Hypercube Interconnection Network
- A Free-space Optical Crossbar Switch Using Wavelength Division Multiplexing and VSCELs
- Multi-Wavelength Optical Content Addressable Parallel Processor (MW-OCAPP)
- Optical Interconnects for the Design of Large Scale Symmetric Multiprocessors
- Reliable and Fault-Tolerant Network-on-Chips for Multi-Core Architectures and Embedded Systems
- Heterogenous Interconnect Technologies (Photonics, 3D Stacking, RF) for Scalable NoCs
- Optical Processing Techniques for High Speed Searching and Matching Applications
- Scalable Cache Coherent Scheme for Distributed Shared Memory Systems
- Optical Switching Fabrics for Scalable IP Routers
- Multi-Domain Modeling and Simulation of Optical Interconnects for Multiprocessor Application
- Design of Reconfigurable and Scalable Optical Interconnection Networks for Balanced Parallel Computing Systems
- Performance-Adaptive and Power-Aware Hybrid Opto-Electronic Interconnects for HPCs
- Nano-Photonics for Network on Chips
HPCAT Members
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Md Farhadur Reza
Ph.D
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Hao Zheng worked on building a power-efficient Network-on-Chips (NoCs). His primary research interests are energy and performance optimization of the multi-core system.
Hao Zheng
Ph.D Student
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Priyankar is investigating how to implement emerging optical technologies in interconnects of data centers as well as in main-stream computer architecture to achieve better performance.
Priyankar Royhowdhury
Ph.D Student
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Ke’s research area lies on machine learning and NoCs design. The goal is to find an optimized NoC design of high performance, power efficiency and reliability by applying machine learning algorithms.
Ke Wang
Ph.D Student
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Jie’s research direction lies on deep neural networks and accelerator design. Her primary research interest is to design an adaptive and energy-efficient accelerator for convolutional neural networks. The goal is to make the neural network accelerator feasible to power-constrained devices.
Jie Luo
Ph.D Student
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Yuechen’s research area lies in NoC design and big data application. As NoC performance is critical in multi-core CPU design, he believes, the combination of hardware and software design will deliver high performance.
Yuechen Chen
Ph.D Student
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Ruhong is currently pursuing my MS in VLSI studies. In 2017 spring, He began researching in Prof. Louri’s lab. His project will be focused on buffer design of Router in NOC, optimizing resource allocation with optimized allocation strategy.
Ruhong Kang
Graduate Student
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Yi is pursuing his MS in Computer Architecture and he joined Prof. Louri’s Lab in late 2017. Yi’s current project is focus on NoC design, such as topology and routing algorithm, to get low cost, high performance and energy-efficient.
Yi Zhao
Graduate Student
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Yuan Li is working on 3D Network-on-Chip architectures. His research aims to facilitate high performance computing with novel architectures and mechanisms.
Yuan Li
Graduate Student
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Sebastian is a Computer Engineering major graduating in 2019. In 2018, he will be at NVIDIA, writing systems code for self-driving cars. In 2017 he worked in the Platform Engineering Group at Intel. His interests are systems and computer architecture.
Sebastian Foubert
Undergrad Student
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Computer Enginnering Class of 2019. Parmvir assists the laboratory in researching Network-on-Chips (NoCs) via tools such as WinMIPS. In addition, he aids the Graduate Research Assistants by maintaining a database of the sources.
Parmvir Chahal
Undergrad Student
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Computer Engineering Class of 2020. Sophia is a second year student majoring in Computer Engineering. Although she is just starting to learn the basics, she is mostly interested in Computer Organization and Architecture
Sophia Martinez
Undergrad Student
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Marie-Laure is majoring in Computer Engineering and is graduating with the class of 2019. She is most interested in computer architecture and organization as well as systems.
Marie-Laure Brossay
Undergrad Student
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